1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, the present invention relates to a structure of a thin film transistor (TFT) applicable to a liquid crystal display (LCD) panel and a manufacturing method of the TFT structure.
2. Description of Related Art
Since the polysilicon thin film transistor (poly-Si TFT) has advantages such as low power consumption and high electron mobility compared with the amorphous silicon thin film transistor (a-Si TFT), the low temperature polysilicon thin film transistor (LTPS-TFT) has been extensively adopted in large-sized liquid crystal displays (LCDs).
Referring to FIG. 1, which is a schematic cross-sectional view illustrating a conventional LTPS-TFT. As illustrated in FIG. 1, a buffer layer 102 is formed on the substrate 100, and a polysilicon layer 110 is formed on the buffer layer 102. The polysilicon layer 110 includes a source region 112 and a drain region 114 formed by a doping process, and a channel region 116 is located between the source region 112 and the drain region 114.
Still referring to FIG. 1, a gate insulation layer 120 covers the polysilicon layer 110 and the buffer layer 102, and a gate 130 is disposed on the gate insulation layer 120 over the channel region 116. A dielectric layer 140 covers the gate 130 and the gate insulation layer 120, and contact windows 112a and 114a are formed in the dielectric layer 140 and the gate insulation layer 120. In addition, a source metal layer 152 and a drain metal layer 154 are disposed on the dielectric layer 140. The source metal layer 152 and the drain metal layer 154 are electrically connected to the source region 112 and the drain region 114 through the contact windows 112a and 114a respectively.
It should be noted that in order to lower a lateral electric field during operation of transistors so as to increase the reliability of devices and reduce the possibility of current leakage, a lightly doped drain (LDD) region 118 is usually formed among the source region 112, the drain region 114 and the channel region 116. During a conventional manufacturing process of a polysilicon TFT having the LDD region 118, it usually takes more than two mask processes and more than two doping processes to form the source region 112, the drain region 114 and the LDD region 118 with different dopant concentrations. However, the aforesaid method of manufacturing an LDD region not only has a more complicated manufacturing process but also creates more difficulty in aligning mask patterns, such that the formed TFTs have different electrical performances and thereby affects the reliability of products.